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2006年10 期
| 標(biāo)題 |
| 基于FPGA/CPLD的高速和低速UART的設(shè)計(jì)及其應(yīng)用(15 卷) |
| 英文標(biāo)題 |
| Design and application of high speed and low speed UART based on FPGA/CPLD |
| 摘要 |
| 利用計(jì)算機(jī)軟件技術(shù)（EDA技術(shù)）和FPGA/CPLD的靈活性可以方便快速地設(shè)計(jì)高速和低速的UART。高速的UART可以用在光纖通信上，低速的UART可以用在FPGA/CPLD和單片機(jī)的通信上。設(shè)計(jì)中包含UART的發(fā)送模塊、接收模塊和波特率發(fā)生器，所有功能的實(shí)現(xiàn)全部采用VHDL硬件描述語言來進(jìn)行描 |
| 作者 |
| 新聞作者:王永州，范多旺 |
| 關(guān)鍵字 |
